Augur One is everything your firmware expects to find around it: sensors that answer, loads that push back, buses that respond, and faults that arrive when the agent decides they should.
Testing a control loop means having a plant to close it against, so someone builds one: a sensor breakout on a jumper harness, a motor with a load on it, a bench supply, a logic analyzer, and a person to power-cycle the whole thing when the DUT locks up.
Augur One is that bench as one board. Your DUT board plugs in, and the world your firmware reads is generated in hardware and driven from the network.
Your DUT board carries the part under test and whatever it needs to boot. The connectors bring it everything else.
Emulating a world is two kinds of work, and they want different silicon.
| Sensor register models, bus slaves, PWM and encoder decode, fault injection, capture | Lattice ECP5 FPGA | Timing is decided in gateware, so the DUT's bus is answered at the DUT's clock |
| Plant models, closed-loop state, physics integration | STM32N657, Cortex-M55 | State advances between the DUT's samples |
| The agent, test authoring, verdicts, evidence | Your bench computer | None of it is real-time, so none of it can stall the plant |
The first two rows are Augur One. The third is a Linux machine with gigabit Ethernet that you supply: we do not sell it, and nothing about it is special, so a lab that already has machines does not buy another one.
Power over Ethernet is standard, 802.3bt Type 4: one run of Cat-6 carries both, so a bench is a switch port. USB-C is the backup link and the recovery path when there is no PoE switch on hand.
A dedicated supervisor MCU, an STM32H563, sits on its own rail and owns recovery and DUT power. The board is built around one rule: Ethernet must not drop while something is being recovered. So the FPGA and the real-time MCU are always powered, and every recovery path is a reset.
Watch an agent run a task on the bench.
Neither the FPGA nor the real-time MCU has a power switch anywhere on the board, so half-powered states do not exist to get stuck in. That comes from the schematic, not from firmware discipline.
Every figure above, part by part.
See the full specification| FPGA | Lattice ECP5 LFE5U-85F. Protocol, capture, fault injection. |
| Real-time MCU | STM32N657, Cortex-M55. Physics and plant state. Carries an NPU, unused today: headroom for physics too expensive to integrate directly. |
| Supervisor | STM32H563. Recovery and DUT power. |
| Wireless peer | ESP32-C5. Wi-Fi and Bluetooth LE, so the bench is the other end of the DUT's link. |
| Digital I/O | 148 pins across 4 banks, each bank on its own adjustable 1.2–3.3 V rail. Driven from gateware, so any pin can be SPI, I2C, UART, CAN, PWM, an encoder channel, or whatever protocol your part speaks. |
| Debug | SWD or JTAG, driven from the FPGA onto any DUT I/O pin. No fixed debug pinout to design around. |
| DUT supply | 1.8–5 V adjustable, Kelvin-sensed. Current is sensed on two ranges: 250 µA resolution up to 8.19 A for normal draw, and 31 nA resolution on the low range for sleep currents. |
| Ethernet to the DUT | 3 x gigabit, 4-pair MDI |
| USB to the DUT | 2 x USB 2.0 OTG, with software-controlled attach |
| Wireless to the DUT | ESP32-C5 test peer on board: Wi-Fi and Bluetooth LE. The bench is the other end of the link, so pairing, association and dropped connections are all things a test can do on purpose. |
| DUT self-ID | 11 straps read at power-up: 4 bits of board revision, 4 bits of capability flags, 3 bits selecting the supply the board expects. An unprogrammed board reads all ones and the bench treats it as unknown rather than powering it. |
| Channels | Up to 40, as 10 slots of 4, and additional to the 148 digital pins. Each slot takes a high-speed or a medium-speed module, mixed freely. Populate only the slots you need. |
| High-speed module | 2 x AD3542R per slot, on dedicated +7 V and -1.5 V rails. For channels the control loop reads at rate. |
| Medium-speed module | DAC80504 per slot. For channels that move slowly: temperatures, pack voltages, setpoints. |
| Signal integrity | Every analog channel is flanked by its own analog-ground return. No analog line has an analog neighbour. |
| Gigabit Ethernet | Power and network on one cable. 802.3bt Type 4 PoE. |
| USB-C | Backup link and recovery |
Interface figures are counted from the built netlist rather than a block diagram. Converter figures come from the parts named above.
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