The loop

One prompt. Four iterations. PASS.

Wire test first, logic analyzer on the bus, the emulated world catching what the bus can't. Recreated from the bench flow, sped up; Betaflight already flies against this same FPGA fabric.

oracova bench replay · recreated · sped up · not live video

$ oracova task "implement and test the gyro driver"

plan MPU6000 gyro/accel · SPI1: 1 MHz cfg / 20 MHz data · DUT STM32F411, real silicon

world pulling mpu6000 model from the marketplace (validated verilog)

synth → bench FPGA .......................... ok

bench DUT board seated · internal logic analyzer armed on SPI1

netlist parse DUT board PCBA: SPI1 → PA5 SCK · PA6 MISO · PA7 MOSI · PA4 nCS

map DUT pins → base connector → FPGA balls ............ 4 nets routed

wiretest gpio loopback, no protocol: fabric drives each net, edge counters at the far end

PA5 ✓ PA6 ✓ PA7 ✓ PA4 ✓ 4/4 nets toggle · 0 shorts · 0 opens

bench wiring is ground truth — every failure after this line is firmware

iter 1 write driver: spi init · burst read WHO_AM_I @ 10 MHz

build ok flash ok test running

who_am_i ................................. FAIL read 0xFF, expected 0x68

internal logic analyzer · spi1 · iter 1

Config read clocked at 10 MHz. This part caps register reads at 1 MHz — 20 MHz is data-only.

la WHO_AM_I clocked at 10 MHz — register reads cap at 1 MHz on this part

fix config bus → 1 MHz (sensor burst stays 20 MHz) → rebuild

iter 2 flash ok · test running

who_am_i ................................. PASS 0x68

gyro_x .................................... FAIL reads 0x0000, always

internal logic analyzer · spi1 · iter 2

bit 7 = 0 → that's a write, not a read. The 0x80 read flag is missing.

la addr 0x43 sent without the 0x80 read bit

fix set MSB on register reads → rebuild

iter 3 flash ok · test running

gyro_x .................................... data flows

rate check: world spins the table 90 °/s · driver reports 11.3

fix scale: driver assumed 131 LSB/(°/s), device is FS_SEL=3 → 16.4

iter 4 flash ok · full suite

who_am_i .................................. PASS

self test ................................. PASS

rate step 90 °/s .......................... PASS

burst read @ 8 kHz sustained .............. PASS

verdict PASS 4 iterations · 6 m 42 s unattended

checker deterministic, fixed thresholds — the agent never grades its own work

task · implement and test the gyro driver

This is the same loop every board gets: netlist in, wire truth, then implement → flash → test → probe → fix until the deterministic checker says PASS. See a scored run report →